Advanced Electronics Assembly on a Miniature Scale

Beyond BGAs, another common miniaturization technique is the use of wafer level chip scale packages. Wafer level chip scale packages (WLCSPs) 

are essentially micro-scale ICs mass-created on a wafer that are later diced into an individual IC-containing die or chips of a few millimeters in 

length and width. Here, the connections are made of solid gold joints, either gold bumps or gold wire bonds. These gold joints maintain their 

reliability when they are as small as 30 microns in diameter; they can be placed a couple of microns apart.

As the size of transistor nodes goes down, chips can further be downsized without compromising performance. Sometimes their performance

can even increase as they get smaller. These smaller transistor nodes are what enable the more robust system-on-chip (SoC), which can carry 

out more tasks with better performance.

Like BGAs, the connections on the IC die are usually accessed on the underside of the chip, but that can vary by chip design. This flexibility 

makes IC chips more versatile, but it also makes the advanced electronic assembly process needed to integrate them more intricate. The 

process needed to interface them into their intended devices has also become more involved. This is where art meets science- enter the 

Chip on Board (CoB) process.